The present invention relates to a method for manufacturing a semiconductor device formed in a semiconductor layer provided on an insulator, and a MOS field effect transistor formed in a semiconductor layer provided on an insulator.
There has heretofore been known a so-called SOI integrated circuit wherein an elemental device such as a transistor is formed in a silicon semiconductor layer by using an SOI (Silicon On Insulator) substrate in which the silicon semiconductor layer is laminated on an insulator.
The SOI integrated circuit is superior to an integrated circuit (hereinafter called “silicon integrated circuit”) formed in a single silicon substrate in that, for example, (1) it is small in parasitic capacitance and excellent in high-speed performance, (2) it is resistant to soft errors, (3) no latch up occurs and (4) a well process can be omitted.
In the SOI integrated circuit, particularly, a MOS field effect transistor (hereinafter called “SOI-MOSFET”) formed in an SOI substrate, the SOI-MOSFET is placed in a state of being electrically isolated by field oxide films for device isolation, and an insulator that constitutes the SOI substrate. Therefore, holes generated by collisions (impact ionization) between electrons accelerated by an electric filed in the vicinity of a drain region and lattice atoms are stored in a channel region. Described more specifically, the holes are not able to escape to a source region due to an energy barrier between the source region and the channel region, thus resulting in the storage thereof in the channel region. Various phenomena generated by storage of the holes in the channel region are called “floating body effects”.
As one of the floating body effects, may be mentioned, single latch up. The single latch up means that the potential of the channel region rises due to the storage of the holes, so that the source region, the channel region and the drain region apparently operate as a bipolar transistor. The single latch up causes an increase in current that flows through the channel region, thus resulting in the occurrence of a reduction in drain breakdown voltage of the SOI-MOSFET. Problems such as the single latch up, the reduction in the drain breakdown voltage with the latch up, etc. come to the fore where the voltage applied to the drain region is high.
In order to solve these problems with the floating body effects, there has been known a prior art wherein Ar ions or the like are implanted in a source region and a drain region to artificially form crystal defects in a silicon semiconductor layer, and the crystal defects are constituted as recombination centers of holes (refer to, for example, a patent document 1 (Japanese Unexamined Patent Publication No. Hei 11(1999)-74538 (FIG. 4), and a patent document 2 (Japanese Unexamined Patent Publication No. 2001-326361 (FIG. 2)).
The methods for introducing the crystal defects in the silicon semiconductor layers respectively, which have been disclosed in these patent documents 1 and 2, are capable of effectively suppressing the floating body effects. With the recent miniaturization of a semiconductor device, however, a new problem also arises with derivation from the crystal defects.
The new problem resides in an increase in off-leakage current of the SOI-MOSFET. Here, the off-leakage current indicates a current which flows between the source region and the drain region when the voltage applied to its gate is 0V, the source region is grounded and a predetermined voltage is applied to the drain region.
The cause of the increase in the off-leakage current resides in that a thermal treatment temperature for activating dopants with the miniaturization of each SOI-MOSFET is rendered lower than ever.
The increase in the off-leakage current of the SOI-MOSFET will be explained below.
When the gate length the SOI-MOSFET is reduced, a short channel effect occurs. The short channel effect means a phenomenon in which the influence of an electric field in the drain region is exerted even upon the source region so that the threshold voltage of the field effect transistor is reduced.
In order to suppress the short channel effect, it is effective to hold long a channel length corresponding to an interval between the source region and the drain region. To this end, there is a tendency to lower an anneal temperature for activating dopants introduced into a source forming predeterminate area or region and a drain forming predeterminate area. That is, the diffusion of the dopants in a gate-length direction is suppressed by execution of anneal at the low temperature. As a result, a channel length simply necessary for the suppression of the short channel effect can be ensured.
When, however, the anneal temperature is lowered, crystal defects derived from ion implantation of Ar are not recovered sufficiently, and a large number of crystal defects remain in the silicon semiconductor layer. As result, a current leaks between the source regions and the drain region through the crystal defects in the SOI-MOSFET. That is, the off-leakage current increases.
In order to solve such a problem, the present inventors have carried out investigations and experiments diligently and have found clues to the solution of the problem.
Results (FIGS. 6 and 7) of experiments carried out by the present inventors are shown below, and the problem of the above SOI-MOSFET will be explained in further detail. Here, FIG. 6 is a view showing flowcharts illustrative of major process steps in processes for manufacturing SOI-MOSFETs employed in the present experiments. FIG. 7 is a view showing the characteristics of the SOI-MOSFETs employed in the present experiments.
Upon execution of the present experiments, three types of SOI-MOSFETs shown below were manufactured by varying manufacturing process steps.
The SOI-MOSFET (hereafter called “FET1”) shown in FIG. 6(A) is fabricated by the known method except that anneal for activating dopants ion-implanted in a source forming predeterminate area and a drain forming predeterminate area is carried out at a temperature (975° C. for 10 seconds) lower than ever (about 1050° C. for 10 seconds). Incidentally, the ion implantation of Ar for suppressing a floating body effect is not effected on the FET1.
The SOI-MOSFET (hereinafter called “FET2”) shown in FIG. 6(B) is manufactured by a method similar to the FET1 except that after the ion implantation of Ar and the ion implantation of the dopants, once anneal (975° C. for 10 seconds) is carried out. That is, the FET2 simultaneously performs the recovery of crystal defects derived from the Ar ion-implantation and the activation of the dopants at the above once anneal. Here, Ar ion-implantation conditions for the FET2 are as follows: implantation rate: 2×1014 cm−2 and implantation energy: 30 keV.
The SOI-MOSFET (hereinafter called “FET3”) shown in FIG. 6(C) is different from the FET2 in that the ion-implantation rate of Ar is smaller than that at the FET2. Here, Ar ion-implantation conditions for the FET3 are as follows: implantation rate: 5×1013 cm−2 and implantation energy: 30 keV.
Even in the case of any of FET1 through FET3, its gate length is 0.35 μm.
In FIG. 7, any of the vertical axes shows a drain current Id(A) per gate width 1 μm, and any of the horizontal axes in FIG. 7 shows a gate voltage Vg(V). Nine graphs drawn in FIGS. 7(A) through 7(C) respectively correspond to different drain voltages Vd(V). Although shown even in the figures, the drain voltages Vd are varied at 0.4V intervals from 0.1V to 3.3V.
As shown in FIG. 7(A), the respective graphs are spaced away from one another in FET1. When the graphs are respectively seen on the whole, their transverse widths become wide. This results from floating body effects. Now consider a difference ΔVg (=Vgmax−Vgmin) between the maximum value Vgmax of a gate voltage Vg at Id=0.1 μA and its minimum value Vgmin as an index indicative of the transverse width of the entire graph, i.e., an index indicative of the magnitude of the floating body effect. From the graph of Vd=0.1V, Vgmax can be read as about 0.7V. Similarly, Vgmin can be read as about 0.1V from the graph of Vd=3.3V. Thus, ΔVg results in about 0.6V (=0.7−0.1).
On the other hand, as shown in FIG. 7(B), the transverse widths of the respective graphs become narrow as compared with FET1 on the whole in the case of FET2 subjected to the ion implantation of Ar. ΔVg at FET2 is about 0.3V and is narrowed by about 0.3V in width as compared with FET1. This means that crystal defects derived from the ion implantation of Ar function as recombination centers of holes, and floating body effects are suppressed.
It is however understood that an off-leakage current Idoff (Id at Vg=0V) of FET2 is larger than FET1 on the whole. At Vd=3.3V in particular, an off-leakage current Idoff of a few pA or so occurs. This means that in the case of the above anneal (975° C. for 10 seconds), the crystal effects derived from the Ar ion-implantation are not recovered sufficiently, and a current leaks between a source region and a drain region through the crystal defects.
The results up to now are summarized as follows. It is understood that when the anneal temperature is 975° C., the ion implantation of Ar is carried out and in the case of FET2 in which the crystal defects are artificially introduced, the floating body effects are suppressed, whereas the off-leakage current Idoff increases.
From this result, the present inventors have considered that the suppression of the floating body effects and the reduction in the off-leakage current can be simultaneously attained if the ion-implantation rate of Ar is decreased to reduce the quantity of the crystal defects introduced into the silicon semiconductor layer, and then have fabricated FET3 in which the implantation rate of Ar ions is reduced, thereby obtaining a result shown in FIG. 7(C).
In the case of FET3 in which the ion-implantation rate of Ar is set to ¼ of FET2, as shown in FIG. 7(C), the maximum value of the off-leakage current Idoff ranged from 2 pA to 3 pA (from the graph at Vd=3.3V), and ΔVg indicative of the index of the floating body effect was about 0.5V.
When FET3 and FET2 are compared with each other, the off-leakage current Idoff is reduced by a rate commensurate with a decrease in the ion implantation of Ar, whereas the substrate floating effect greatly increases to such a degree as to become near that at FET1.
It has been revealed from this that the mere decrease in the ion-implantation rate of Ar encounters difficulties in simultaneously attaining the suppression of the floating body effects and the reduction in the off-leakage current Idoff.